Modern dielectric patterning schemes, which allow the formation of metal conductors in the form of lines and vias, may be based on a dual damascene process. In one manifestation, this process may allow the formation of metal conductors from patterned vias and lines in a single metallization step, followed by the removal of excess metal by chemical-mechanical polishing (CMP). Due to the subtractive nature of this process (i.e., a blanket layer of the dielectric is typically patterned (material removal) by dry etch processes prior to metal deposition), the interlayer dielectric insulator (ILD) may be exposed to different etch chemistries, some of which can be very damaging to the ILD. An additional layer, generally referred to as a hardmask (HM), may need to be deposited on top of the ILD to allow for good pattern transfer control, photoresist (PR) rework as well as acting as a polish stop during CMP. This hardmask should exhibit good etch contrast with respect to the underlying ILD and adhere well to the dielectric material. Example hardmask materials include SiO2, SiN and TiN.